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微商城网站建设哪家好,无忧网站,重庆网站模板建站公司,免费做房产网站一、FPGA如何实现延时 1.关于ps级别的延时 2.关于ns级别的延时 3.关于10ns级别的延时 4.关于1ms级别的延时参考#xff1a;https://www.baidu.com/link?urlsojRDWma1MokFTKgGgf-i-d2hLSTZg2HX45zu5TtJ1YlmEATIqwTc6NexEPZIozYA314EHQVPEYFcWGDBOGFZXGVsz-i1kSbTa6KuoHIJm_https://www.baidu.com/link?urlsojRDWma1MokFTKgGgf-i-d2hLSTZg2HX45zu5TtJ1YlmEATIqwTc6NexEPZIozYA314EHQVPEYFcWGDBOGFZXGVsz-i1kSbTa6KuoHIJm_wdeqid89e7a2d40503cda6000000066948d8ee参考https://baijiahao.baidu.com/s?id1827942128414919469wfrspiderforpc参考https://blog.csdn.net/gaoxcv/article/details/124591638使用carry进位链实现ps级别延时参考http://www.360doc.com/content/25/0926/10/64556539_1162023558.shtml参考https://blog.csdn.net/ipfs8storage/article/details/154445402(* keep_hierarchy TRUE *)module TDL#(parameter NUM_STAGES 264)(//InputsiRST,iHIT,iSTORE_STOP,//OutputsoTHERMOMETER_VALUE,oFED);//Singal type definition//Inputsinput iRST;input iHIT;input iSTORE_STOP;//Outputsoutput [NUM_STAGES - 1 : 0] oTHERMOMETER_VALUE;output oFED;// Define interenal signals(* dont_touch TRUE *) wire [NUM_STAGES - 1 : 0] wFIS_VALUE;(* dont_touch TRUE *) wire STORE_STOP_BUFG;/*(* dont_touch TRUE *)*/ wire wFED;wire [NUM_STAGES - 1 : 0] rVALUE;BUFG bufg_inst (.I(iSTORE_STOP), // 输入时钟信号.O(STORE_STOP_BUFG) // 输出缓冲后的时钟信号);//FINE TDC DELAY CHAINgenvar i;generatefor(i 0 ; i (NUM_STAGES / 4) - 1; i i 1)begin : generate_blockif(i 0)begin : CARRY4_first(* dont_touch TRUE *)CARRY4 CARRY4_first_inst(.CO (wFIS_VALUE[3 : 0]), // 4-bit carry out.O (),.CI (1b0), // 1-bit carry cascade input.CYINIT (iHIT), // 1-bit carry initialization.DI (4b0000), // 4-bit carry-MUX data in.S (4b1111) // 4-bit carry-MUX select input);endelsebegin : CARRY4_others(* dont_touch TRUE *)CARRY4 CARRY4_others_inst(.CO (wFIS_VALUE[4 * (i 1) - 1 : 4 * i]),.O (),.CI (wFIS_VALUE[4 * i - 1]),.CYINIT (1b0), //0表示加法1表示减法.DI (4b0000),.S (4b1111));endendendgenerate//FIRST STAGE D FLIP FLOPS TO SAMPLE DELAY CHAINgenvar j;generatefor(j 0 ; j NUM_STAGES - 1 ; j j 1)begin(* dont_touch TRUE *)FDCE #(.INIT(1b0)) rTDC_VALUE(.Q (rVALUE[j]),.C (STORE_STOP_BUFG),.CE (1b1),.CLR (iRST),.D (wFIS_VALUE[j]));endendgenerateassign wFED wFIS_VALUE[0];assign oFED wFED;assign oTHERMOMETER_VALUE rVALUE;endmodule二、FPGA实现频率计1.使用FPGA统计信号的长度https://blog.csdn.net/SLAM_masterFei/article/details/105582220三、FPGA实现延时短延时10nsIDELAYE2硬核 寄存器打拍中延时10ns~1ms计数器 移位寄存器长延时1msFIFO外部DDR 大容量BRAM皮秒级需求PLL相位插值 IDELAYE2皮秒级需求使用carry4或者carry8进位链来实现皮秒级需求FPGA的DSP来实现延时